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MYSON TECHNOLOGY
FEATURES
* * * * * * * * * * * * IEEE802.3 and IEEE802.3u compliant. Provide 4 RMII and 1 MII/RMII ports. Programmable 1K/8K MAC addresses filtering. Store and forward switching function and bad packet filtering function. Optional back_pressure/802.3x flow control/ flooding control/broadcast control. Optional EEPROM Interface for advanced switch configurations. 1MB/2MB SGRAM/SDRAM flexible memory interface. Port VLAN/trunking. Link/Rx activity, packet buffer utilization LED display. 50MHz for non-blocking for 5 ports switch operation Build in internal/external memory test function. 128 pin PQFP package, 3.3V operation voltage.
MTD505 (Preliminary)
GENERAL DESCRIPTION
The MTD505 complies fully with the IEEE802.3, 802.3u and 802.3x specifications and is a non-blocking 5 port 10M/100M Ethernet switch device. Support 4 RMII and 1 MII/RMII ports for 10M/100M operation. 1MByte/2MBytes memory interface provides maximum 1365 packet buffers for Ethernet packet buffering. Up to 8192 address entrys are provided by the MTD505, and the MTD505 use full Ethernet address compare algorithm to minimize hashing collision events. The MTD505 provides EEPROM interface to config port trunking, port VLAN, static entry, 802.3x flow control threshold, flooding port, broadcast control threshold. Each MTD505 port support 10/100M auto-negotiation by MDC/MDIO interface for connecting external PHY devices. The MTD505 also provides 10 pins for Link/RX activity, packet buffer utilization LED display function.
5 Port 10M/100M Ethernet Switch
BLOCK DIAGRAM
SDRAM/ SGRAM Interface
Memory Controller DMA0 MAC0 RMII0
DMA1
MAC1
RMII1
DMA2 Memory Arbiter
MAC2
RMII2
DMA3
MAC3
RMII3
DMA4
MAC4
RMII/MII4
Port Switch Logic
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product. 1/19 MTD505 Revision 1.2 14/04/2000
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SYSTEM DIAGRAM
MTD505 (Preliminary)
(**Progr ammable) SGRAM (256k32x1)
(**OPTION) EEPROM
SGRAM (512k32x1)
MTD505
SGRAM (256k32x2)
LEDs
RMII0-3
MII4
QUAD PHYsceiver
MII management
Single PHYsceiver
QUAD Transformer
Single Transformer
RJ45
RJ45
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product 2/19 MTD505 Revision 1.2 14/04/2000
1.0 PIN CONNECTION
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LEDDATA4 LEDDATA3 LEDDATA2 LEDDATA1 LEDDATA0 GNDI CLK25M VCCI SDC SDIO EECLK EEDATA RESETB REFCLK MDIO MDC CRSDV0 TXD0_1 TXD0_0 TXEN0 RXD0_0 RXD0_1 CRSDV1 TXD1_1 TXD1_0 TXEN1
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
MTD505
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RXD1_0 RXD1_1 CRSDV2 TXD2_1 TXD2_0 TXEN2 GNDO VCCO RXD2_0 RXD2_1 CRSDV3 TXD3_1 TXD3_0 TXEN3 RXD3_0 RXD3_1 CRSDV4 COL4 TXD4_3 TXD4_2 TXD4_1 TXD4_0 TXEN4 TXC4 RXC4 RXDV4 GNDI VCCI RXD4_0 RXD4_1 RXD4_2 RXD4_3 GNDI VCCI GNDI SYSCLK VCCI DQ31 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 LEDDATA5 LEDDATA6 LEDDATA7 VCCO GNDO LEDCLK2 LEDCLK1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ16 DQ17 DQ18 DQ19 DQ20 VCCO GNDO DQ21 DQ22 DQ23 WEB CASB RASB CS0B BA VCCI GNDI CS1B AD0 AD1 AD2 AD3 AD4
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
MTD505 (Preliminary)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
VCCO GNDO AD5 AD6 AD7 AD8 VCCI MEMCLK GNDI DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ24 DQ25 DQ26 VCCO GNDO DQ27 DQ28 DQ29 DQ30
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2.0 PIN DESCRIPTIONS
RMII/MII Port Interface Pins Name CRSDV0 RXD0_0 RXD0_1 TXEN0 TXD0_0 TXD0_1 CRSDV1 RXD1_0 RXD1_1 TXEN1 TXD1_0 TXD1_1 CRSDV2 RXD2_0 RXD2_1 TXEN2 TXD2_0 TXD2_1 CRSDV3 RXD3_0 RXD3_1 TXEN3 TXD3_0 TXD3_1 CRSDV4 RXDV4 RXCLK4 RXD4_3 RXD4_2 RXD4_0 RXD4_1 TXEN4 TXCLK4 Pin Number 119 123 124 122 121 120 125 01 02 128 127 126 03 09 10 06 05 04 11 15 16 14 13 12 17 26 25 32 31 29 30 23 24
MTD505 (Preliminary)
I/O Descriptions I Port0 RMII receive interface signal, CRSDV0 is asserted high when port0 media is non_idle. I Port0 RMII receive data bit_0. I O O O I I I O O O I I I O O O I I I O O O I I I I I I I O I Port0 RMII receive data bit_1. Port0 RMII transmit enable signal. Port0 RMII transmit data bit_0. Port0 RMII transmit data bit_1. Port1 RMII receive interface signal, CRSDV1 is asserted high when port1 media is non_idle. Port1 RMII receive data bit_0. Port1 RMII receive data bit_1. Port1 RMII transmit enable signal. Port1 RMII transmit data bit_0. Port1 RMII transmit data bit_1. Port2 RMII receive interface signal, CRSDV2 is asserted high when port2 media is non_idle. Port2 RMII receive data bit_0. Port2 RMII receive data bit_1. Port2 RMII transmit enable signal. Port2 RMII transmit data bit_0. Port2 RMII transmit data bit_1. Port3 RMII receive interface signal, CRSDV0 is asserted high when port3 media is non_idle. Port3 RMII receive data bit_0. Port3 RMII receive data bit_1. Port3 RMII transmit enable signal. Port3 RMII transmit data bit_0. Port3 RMII transmit data bit_1. Port4 RMII/MII receive interface signal, CRSDV4 is asserted high when port4 media is non_idle. Port4 MII receive data valid. In RMII mode, this pin don't use. Port4 MII receive clock signal. In RMII mode, this pin is not used. Port4 MII receive data bit_3. In RMII mode, this pin don't use. Port4 MII receive data bit_2. In RMII mode, this pin don't use. Port4 RMII/MII receive data bit_0. Port4 RMII/MII receive data bit_1. Port4 RMII transmit enable signal. Port4 RMII transmit clock signal. In RMII mode, this pin is not used.
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RMII/MII Port Interface Pins Name TXD4_3 TXD4_2 TXD4_0 TXD4_1 COL4 CLK25M Pin Number 19 20 22 21 18 109
MTD505 (Preliminary)
I/O Descriptions O Port4 MII transmit data bit_3. In RMII mode, this pin don't use. O O O I O Port4 MII transmit data bit_2. In RMII mode, this pin don't use. Port4 RMII/MII transmit data bit_0. Port4 RMII/MII transmit data bit_1. Port4 MII collision input. In RMII mode, this pin don't use. Port4 MII 25MHz clock output. SGRAM/SDRAM Interface Pins
Name AD[8:0]
Pin Number 59,60,61,62, 65,66,67,68, 69
I/O Descriptions O Memory row/column address bus outputs AD[7:0] are row/column address [7:0].
DQ[31:0]
AD[8] : This pin should connect to SGRAM/SDRAM MSB address bit. 38~42,45~55 I/O Memory data bus ,78~80, 83~95 75 76 77 73 74 70 57 O O O O O O O SGRAM/SDRAM row address select SGRAM/SDRAM column address select SGRAM/SDRAM write enable SGRAM/SDRAM bank select Memory chip select 0 Memory chip select 1 Memory clock output.
RASB CASB WEB BA CS0B CS1B MEMCLK
Note: SGRAM/SDRAM access time: 10 ns (max) LED Interface Pins Name LEDDATA [7:0] Pin Number I/O I/O Descriptions LED data output. These LED pins report Port0~7 Link/Rx activity status using LEDCLK1 strobe , and report packet buffer utilization status using LEDCLK2 strobe. LEDDATA [0] 100,101,102, 103,104,105, 106,107 [1] [2] [3] [4] [5] [6] --[7] --LEDCLK1 LR0 LR1 LR2 LR3 LR4 --LEDCLK2 Uti0 Uti1 Uti2 Uti3 Uti4 --note: LRn: means per port' Link_RxAct status. s Uti0: 5%, Uti1: 10%, Uti2: 20%, Uti3: 35%, Uti4: 50 above . BFull: Buffer almost full alarm signal. Mfail: External memory poer on test failure.
BFull MFail
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LED Interface Pins Name LEDCLK1 LEDCLK2 Pin Number 96 97 I/O I/O I/O
MTD505 (Preliminary)
Descriptions
LED strobe 1 LED strobe 2 Miscellaneous Pins
Name RESETB SYSCLK REFCLK MDC MDIO SDC SDIO EEDATA EECLK VCC
Pin Number 115
GND
I/O Descriptions I System reset input, low active. I Switch core system clock input, using the same clock source with REF36 CLK. 116 I RMII reference clock input, using 50Mhz. 118 I/O MII management clock inout 117 I/O MII management data inout 111 I/O MII register clock inout 112 I/O MII register data inout 114 I/O EEPROM data input 113 I/O EEPROM clock output 08,28,34,37, PWR Power pins 44,58,64,72, 82,99,110 02,27,33,35, GND Ground pins 43,56,63,71, 81,98,108
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MTD505 (Preliminary)
Jummper Configuration After Power On Reset Name LEDDATA[0] LEDDATA[1] LEDDATA[2] LEDDATA[3] LEDDATA[4] LEDDATA[5] LEDDATA[6] LEDDATA[7] Pin Number I/O I/O Descriptions During power on reset duration, these pins are jumper setting pins (pull_hgih = 1, pull_low = 0). LEDDATA[0] : select SGRAM/SDRAM interface , "1" means 256K32 x 1 or 512K32 x 1 is selected. "0" means 256K32 x 2 is selected, default is "1". LEDDATA[1] : config packet buffer size, "1" means 2 M bytes buffer size is selected. "0" means 1 M byte buffer size is selected, default is "0" LEDDATA[2] : enable memory test function, "1" means enable. `0" means disable, default is "1". LEDDATA[3] : enable aging function, "1" means enable. "0" means disable, default is "1". LEDDATA[4] : enable MII polling(MDC/MDIO), "1" means enable. "0" means disable, default is "1". LEDDATA[5] : enable broadcast storm control, "1" means enable. "0" means disable, default is "1". LEDDATA[6] : enable backpressure function (in half mode), "1" means enable. "0" means disable, default is "1". LEDDATA[7] : enable 802.3x flow control function (in full mode) , "1" means enable. LEDCLK1 I/O "0" means disable, default is "1". During power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). LEDCLK1 : select 1K or 8K address entry table, "1" means 8K addres entry is selected. LEDCLK2 I/O "0" means 1K address entry is selected, default is "1". During power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). LEDCLK2 : enable EEPROM interface. "1" means enable. "0" means disable, default is "1".
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Name EEDATA Pin Number I/O I/O
MTD505 (Preliminary)
Jummper Configuration After Power On Reset Descriptions During power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). EEDATA : enable EEPROM auto_load configuration function while EEPROM interface is enabled, "1" means enable. TXEN[2:0] I/O "0" means disable, default is "1". During power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). TXEN[2:0] : uplink port (flooding port) 0 ~7 selection; default is "000". During power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). TXEN[3] : enable flooding control, "1" means enable. TXEN[4] I/O "0" means disable, default is "0". During power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). TXEN[4] : enable VLAN tag 1522 bytes receiving, "1" means enable. SDC I/O "0" means disable, default is "0". During power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). SDC : Port4 MII/RMII interface selection, "1" means Port4 MII interface is selected. EECLK I/O "0" means Port4 RMII interface is selected, default is "0". During power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). EECLK : scan mode enable for debugging purpose, "1" means scan mode enable. MDC I/O "0" means scan mode disable, default is "0". During power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). MDC : fast mode enable for testing purpose, "1" means fast mode enable. "0" means fast mode disable, default is "0".
TXEN[3]
I/O
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3.0 FUNCTIONAL DESCRIPTIONS
MTD505 (Preliminary)
The MTD505 is an 5 ports 10/100 Mbps fast Ethernet switch controller. It is a low cost solution for eight ports fast Ethernet SOHO switch design. No CPU interface is required; After power on reset, MTD505 provide an auto load configuration setting function through a 2 wire serial EEPROM interface to acess external EEPROM device, and MTD505 can easily be configured to support port_trunking, port_ VLAN, static entry, 802.3X flow control threshold setting , flooding port assignment ...etc functions. The following descriptions are MTD505' major functional blocks overview. s
3.1 Packet store and forwarding
The MTD505 use simple store and forward algorithm as packet switching method. Input packet from ports will be stored to external memory first, while packet is good for forward (CRC chech ok, 64Bytes < length < 1518Bytes, not local packets, in the same VLAN group ) , if this packet' DA hits, than forward s this packet to the destination port, otherwise this packet will be broadcasted.
3.2 Learning and Routing
The MTD505 supports 1K or 8K MAC entries for switching. Dynamic address learning is performed by each good unicast packet is completely received. The static address learning is achieved by EEPROM configuration. On the other hand, the routing process is performed whenever the packet' DA is caps tured. If the DA can not get a hit result, the packet is going to switch broadcast or forward to the dedicated port according to the flooding control selction.
3.3 Aging
Only the dynamic address entries are scheduled in the aging machine. If one station does not transmit any packet for a period of time, the belonging MAC address will be kicked out from the address table. The aging out time can be program through the EEPROM auto load configuration. (Default value is 300 seconds)
3.4 Buffer Queue Management
The buffer queue manager is implemented to manage the external shared memory (use SDRAM/ SGRAM) for packet buffering. The main function of the buffer queue manager is to maintain the linked list consists of buffer IDs, which is used to show the corresponding memory address for each incoming packet. In addition, the buffer queue manager monitors the rested free spaces status of the external memory, If the packet storage achieve the predefined threshold value, the buffer queue manager will raise the alarm signal which is used to enable the flow control mechanism for avoiding transmission ID queue overflow happening. MTD505 provide 802.3x flow control in full duplex mode and back pressure control in half duplex mode.
3.5 Full Duplex 802.3x Flow Control
In full duplex mode, MTD505 supports the standard flow control defined in IEEE802.3x standard. It enables the stopping of remote node transmissions via a PAUSE frame information interactoin. When the "802.3x flow control enable" bit is set during power on reset (LEDDATA[7] pin is external pull_high), it enables MTD505 supporting 802.3x flow control function in full_duplex mode; When output port buffer queue' on_using value reach the initialization setting threshold value (recommended Xon_TH = 74' s h when using 2Mbytes external memory; Xon_TH = 2e' when using 1Mbytes external memory), h MTD505 will send out a PAUSE packet with pause time equal to FFF to stop the remote node transmission; When the output port buffer queue' on_using value reduce to the initialization threshold s value(recommended Xoff_TH = 30' when using 2Mbytes external memory; Xoff_TH=18' when using h h 1Mbytes external memory), MTD505 will also send a PAUSE packet with pause time equal to zero to inform the remote node to retransmit packet.
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3.6 Half Duplex Back Pressure Control
MTD505 (Preliminary)
In half duplex mode, MTD505 provide a back pressure control mechanism to avoid dropping packets during network conjection situation. When the "back pressure control enable" bit is set during power on reset (LEDDATA[6] pin is external pull_high), it enables MTD505 supporting back pressure function in half_duplex mode; When output port buffer queue' on_using value reach the initialization setting s threshold value (same with the Xon_TH value), MTD505 will send a JAM pattern in the input port when it senses an incoming packet , thus force a collision to inform the remote node transmission back off and will effectively avoid dropping packets. If the "back pressure control enable" bit is not set, and there is no free buffer queue available for the incoming packets, the incoming packets will be dropped.
3.7 MII Polling
The MTD505 supports PHY management through the serial MDIO/MDC interface. After power on reset, the MTD505 write related abilities to the advertisement register 4 of connected PHY devices and restart the auto_negotiation prcedure via MDIO/MDC interface using the predefined PHY addresses increasingly from "01000"b to "01100"b. The MTD505 will periodically and continuously poll and update the link status and link partner' ability which include speed, duplex mode, and 802.3x flow control s capable status of the connected PHY devices through MDIO/MDC serial interface.
3.8 MAC and DMA engine
The MTD505' MAC performs all the functions in IEEE802.3 protocol, such as frame formatting, frame s stripping, CRC checking, bad packet dropping, defering to line traffic, and collision handling. The MAC Rx_engine checks incoming packets and drops the bad packet which include CRC error, alignment error, short packet (less than 64 bytes), and long packet(more than 1518 bytes or 1522 bytes when the "VLAN tag 1522 bytes receive enable" bit is set during power on reset). Before transmission, The MAC Tx_engine will constantly monitor the line traffic using derfering precedure. Only if it has been idle for a 96 bits time (a minimum interpacket gap time, IPG time), actual transmmission can be started. For the half duplex mode, MAc engine will detect collision; if a collision is detected, the MAC Tx_engine will transmit a JAM pattern and then delay the re_transmission for a random time period determined by the back_off algorithm (MTD505 implements the truncated exponential back_off algorithm defined in IEEE 802.3 standard). For the full duplex mode, collision signal is ignored. The MTD505' DMA engine performs the packets non_blocking transportation between MAC engine s and external memory according to a high speed switching procedure. The switching procedure is completed by address learning/routing process and buffer queue management operation.
3.9 EEPROM interface
MTD505 provide an auto load configuration setting function through a 2 wire serial EEPROM interface to acess external EEPROM device(24C02) after power on reset . MTD505 can easily be configured to support port_trunking, port_ VLAN, static entry, 802.3X flow control threshold setting , flooding port assignment ...etc functions. The following table is the EEPROM contents mapping: Recommended Value Under Basic Operation 8' h13 8' h2c 8' h01 8' hfe 8' hfd 8' hfb 8' hf7 8' hef
MTD505 Revision 1.2 14/04/2000
Name EOB AgeLow AgeHigh VLAN0 VLAN1 VLAN2 VLAN3 VLAN4
EEPROM Address 00 01 02 03 04 05 06 07
EEPROM Content Description Last EEPROM content address value Aging Time bit [7:0] Aging Time bit [15:8] Port0 VLAN register Port1 VLAN register Port2 VLAN register Port3 VLAN register Port4 VLAN register
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Name Reserved Reserved Reserved EEPROM Address 08 09 0a EEPROM Content Description
MTD505 (Preliminary)
Recommended Value Under Basic Operation 8' hdf 8' hbf 8' h7f
reserved reserved reserved bit[7:4] --- the flooding port_no of Port1 bit[3:0] --- the flooding port_no of Port0 *ex1: bit[7:4] = "0011"b, means that if the incomin packet of Port1 got the "un_routed" result, then this incoming packet will be flooded to Port3. *ex2: bit[3:0] = "0111"b, means that if the incomin packet of Port0 got the "un_routed" result, then this incoming packet will be flooded to Port7. (note: set value "4' means flooding to all the hf", other ports; set value "4' h8"~"4' is forbidden) he" bit[7:4] --- the flooding port_no of Port3
UpLink10
0b
8' h0f
UpLink32
0c
bit[3:0] --- the flooding port_no of Port2 (note: set value "4' means flooding to all the hf", other ports; set value "4' h8"~"4' is forbidden) he" bit[7:4] --- reserved
8' h00
UpLink54
0d
bit[3:0] --- the flooding port_no of Port4 (note: value setting "f", means flooding to all the other ports; value setting "8" ~ "e" is forbidden) reserved Broadcast threshold Xon threshold Xoff threshold Disable Port System control byte : bit[0] --- enhanced back pressure enable, bit[7:1] --- reserved. none Address 26 bit[2:0] --- means Port ID Address 25 bit[7:0] ~ Address 20 bit[7:0] --means static SA[47:0] Address 2d bit[2:0] --- means Port ID Address 2c bit[7:0] ~ Address 27 bit[7:0] --means static SA[47:0]
8' h00
Reserved Broadcast TH Xon TH Xoff TH DisPort
0e 0f 10 11 12
8' h00 8' hff 8' h74 8' h30 8' h00 8' h00
System Control 13 Reserved StaticSA1 14 ~1f 20 ~26
StaticSA2
27 ~ 2d
3.10 Port Based VLAN
The MTD505 supports VLAN configuration by port based methodology. One port select the certain ports to form its VLAN group by configuring the VLAN register. The packet (including broadcast packet) is not forwarding to the destination port whose VLAN group is different from the source port.
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3.11 Port Trunking
MTD505 (Preliminary)
The port trunking function can also be implemented by VLAN registers. One trunk port isolates the packet transmitting and receiving from the other trunk ports, which performs a logical trunk topology. The non-trunk port should choose only one trunk port for transmitting, which can achieve the load balancing and maintain the packet sequences.
3.12 Memory Interface
Two kinds of external memory interface can be selected by user -- 1M byte memory (256K32 x 1) and 2 M bytes (256K32 x 2 or 512K32 x 1). Maximum 2M byte external memory can be used for packet buffering. "-10 " speed grade of SGRAM/SDRAM device is recommanded. The following table is the SGRAM application pin connection : Memory Type 256K32 256K32 512K32 Memory Chip No x1 x2 x1 A[8] A8 A8 A9 CS0B CS0B CS0B CS0B CS1B NC CS1B A8
3.13 Internal MII Registers Acess and Control
The MTD505 support 2 serial pins (SDIO/SDC) for internal registers acess and control; The detailed registers informations are presented in Section4.0 (Internal MII Registers).
3.14 LED Display
The MTD505 use 10 pins to output 2 kinds of LED display -- LEDDATA[7:0], LEDCLK1, LEDCLK2. Using LEDCLK1 rising edge, LEDDATA[7:0] report Port7~0 link/receive activity led status. Using LEDCLK2 rising edge, LEDDATA[4:0] report packet buffer utilization rating, and LEDDATA[7] report external memory test result(after power reset, MTD505 will test external SDRAM automatically), LEDDATA[6] report the buffer almost full alarm signal .
4.0 Internal MII Registers
The MTD505 implements 10 MII global registers and 4 per port registers, define as following tables: TABLE 1. MII r egister s GLOBAL REGISTERS REG NO 0 Bits Name CtlReg0 R/W R/W Descriptions CONTROL REGISTER 0 bit[0] = 1 --> switch to port 0 registers bit[1] = 1 --> switch to port 1 registers bit[2] = 1 --> switch to port 2 registers bit[3] = 1 --> switch to port 3 registers 8-0 bit[4] = 1 --> switch to port 4 registers bit[5] = reserved bit[6] = reserved bit[7] = reserved 12-9 15-13 1 CtlReg1 bit[8] = 1 --> switch to global registers scan mode select 3-0 Scan port select R/W CONTROL REGISTER 1
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Default
9' h100
16' h3084
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TABLE 1. MII r egister s GLOBAL REGISTERS REG NO Bits 7-0 Name XON R/W XON threshold. XOFF threshold. Descriptions
MTD505 (Preliminary)
Default
15-8
XOFF
While EEPROM is enabled, this register' content will s be updated by EEPROM read XON/XOFF threshold data automatically. After EEPROM read is done, this register can be read/write by management cmd. default is 16' h3084(2M memory) or 16' h1838(1M memory) R/W CONTROL REGISTER 2 bit[15:0] can specify aging time. While EEPROM is enabled, this register' content will s be updated by EEPROM read Aging timer data automatically. After EEPROM read is done, this register can be read/write by management cmd. R/W CONTROL REGISTER 3 bit[15:12] specify port 3' uplink port ID. s bit[11:8] specify port 2' uplink port ID. s bit[7:4] specify port 1' uplink port ID. s
2
CtlReg2
16' d300
15-0
Aging
3
CtlReg3
16' h000f
15-0
Uplink reg0
bit[3:0] specify port 0' uplink port ID. s default is 16' h000f. P.S this register' write sequence is Jumper setting ==> s EEPROM content ==> MII management command. R/W CONTROL REGISTER 4 bit[15:12] :reserved bit[11:8] : reserved bit[7:4] : reserved
4
CtlReg4
16' h0
15-0
Uplink reg1
bit[3:0] specify port 4' uplink port ID. s default is 16' h0. P.S this register' write sequence is Jumper setting ==> s EEPROM content ==> MII management command. R/W CONTROL REGISTER 5 bit[7:0] specify broadcast threshold. bit[8] enable enhance backpressure. Reserved. P.S this register can be writed by EEPROM content or MII management command too.
5 7-0 8 15-9 6 7-0
CtlReg5
16' hff
StsReg0
RO/ RC
STATUS REGISTER 0 bit[4:0] outputs port4-0 RXDMA fifofull, bit[7:5] : reserved.
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TABLE 1. MII r egister s GLOBAL REGISTERS REG NO Bits 15-8 7 StsReg1 RO Name R/W Descriptions
MTD505 (Preliminary)
Default
bit[12:8] outputs port4-0 TXDMA TPUR(fifoempty), bit[15:13] : reserved. STATUS REGISTER 1 0 BufBistDone. 1 2 3 4 5 6 7 8 9 10 BufBistErr. BufInitDone. AddrTblBistDone. AddrTblBistErr. LthTblBistDone. LthTblBistErr. MemBistDone. MemBistErr. EEDone. FreeCntIs0.
8 7-0 15-8 9 7-0 15-8
CtlReg7
R/W
15-11 Reserved. CONTROL REGISTER 7 bit[4:0] output mii polling port4-0 flow control information, bit[7:5] : reserved bit[12:8] output mii polling port4-0 link information, bit[15:13] : reserved.
CtlReg8
"1" means flow control enable or link good. R/W CONTROL REGISTER 8 bit[4:0] output mii polling port4-0 speed information, bit[7:5] : reserved. bit[12:8] output mii polling port4-0 full information, bit[15:13] :reserved. "1" means 100M or full duplex. PORT REGISTERS RO STATUS REGISTER 1 bit[10:0] output Port Tx queue head value. Reserved. RO STATUS REGISTER 2 bit[10:0] output Port Tx queue tail value. Reserved. RO STATUS REGISTER 3 bit[10:0] output Port Tx queue count value. Reserved. R/W CONTROL REGISTER 1 bit[7:0] select Port VLAN group. Reserved.
1 10-0 15-11 2 10-0 15-11 3 10-0 15-11 4 7-0 15-8
StsReg1
StsReg2
StsReg3
CtlReg1
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"R/W" means read/writable.
MTD505 (Preliminary)
5.0 Electrical Characteristics
5.1 Absolute Maximum Ratings
Symbol Parameter VCC Power Supply Voltage VIN Input Voltage VOUT TSTG Output Voltage Storage Temperature RATING -0.3 to 3.6 -0.3 to Vcc+0.3 -0.3 to Vcc+0.3 -55 to 150 Unit V V V
C
5.2 Recommended Operating Conditions
Symbol VCC Power Supply VIN Input Voltage Tj Parameter Min. 3.0 0 0 -40 Typ. 3.3 25 25 Max. 3.6 Vcc 115 125 Unit V V

Commercial Junction Operating Temperature Industrial Junction Operating Temperature
C C
5.3 DC Electrical Characteristics
Symbol Parameter IIL Input Leakage Current IOZ Tri-state Leakage Current CIN COUT CBID3 VIL VIH VOH VOL RI Input Capacitance Output Capacitance Bi-direction buffer Capacitance Input Low Voltage Input High Voltage Output High Voltage Output Low Voltage Input Pull-up/down resistance CMOS CMOS IOL=2,4,8,12,16,24mA IOH=2,4,8,12,16,24mA VIL=0V or VIH=VCC 2.4 75 0.7*Vcc 0.4 2.7 2.7 Conditions no pull-up or down Min. -1 -1 2.8 4.9 4.9 0.3*Vcc Typ. Max. 1 1 Unit uA uA pF pF pF V V V V KOhm
(Under recommended operating conditions and Vcc = 3.0 ~ 3.6V, Tj = 0 to +115 oC)
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5.4 Electrical Characteristics
FIGURE 1. RMII timing REFCLK CRSDV RXD[1:0] TXEN TXD[1:0] T1 T2 Valid T3 T4 Valid
MTD505 (Preliminary)
Symbol T1 T2 T3 T4
Parameter RMII input setup time RMII input hold time RMII output setup time RMII output hold time FIGURE 2. MII timing
Min. 1 1 3 5
Typ.
Max.
Unit nS nS nS nS
Note
RXCLK0 CRS0/RXDV0 RXD0[3:0] TXCLK0
T5 T6 Valid
T7 TXEN0 TXD0[3:0]
T8 Valid
Symbol T5 T6 T7 T8
Parameter MII input setup time MII input hold time MII output setup time MII output hold time
Min. 10 10 3 5
Typ.
Max.
Unit nS nS nS nS
Note
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FIGURE 3. Memor y Wr ite Timing MEMCLK T6 T7 RASB CASB WEB T6 T7 AD[8:0] DQ[31:0] Valid T6 T7 T5
MTD505 (Preliminary)
T8
Valid T6 T7
Valid
Symbol Parameter T5 Memory clock cycle Memory command/address/data T6 setup time Memory command/address/data T7 hold time T8 Row active to burst write
Min. 12 6 2
Typ.
Max.
Unit nS nS nS
Note
2
CLK
FIGURE 4. Memor y Read Timing
MEMCLK T6 T7 RASB CASB WEB T6 T7 AD[8:0] DQ[31:0] Valid
T5
T8
T6
T7
Valid T9 T10 Valid
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MYSON TECHNOLOGY
Symbol Parameter T10 Memory read data setup time T11 Memory ead data hold time Min. 2 2 Typ. Max.
MTD505 (Preliminary)
Unit nS nS Note
FIGURE 5. EEPROM timing T11 EECLK T12 EEDATA Valid T13
Symbol Parameter T11 EEPROM clock cycle T12 EEDATA input setup time T13 EEDATA input hold time
Min. 1 1
Typ. 10
Max.
Unit uS nS nS
Note
FIGURE 6. LED Inter face LEDCLK1 T14 LEDCLK2 T15 LEDDATA Valid T16 Valid Valid
Symbol Parameter T14 Led display strobe period T15 LEDCLK setup time T16 LEDCLK hold time
Min.
Typ. 20 5 5
Max.
Unit uS uS uS
Note
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MTD505 Revision 1.2 14/04/2000
MYSON TECHNOLOGY
6.0 128 pin PQFP Package Data
MTD505 (Preliminary)
D1 D 102 103 65 64
Symbol A A1 A2 B C D D1
E1
Dimension in inch Min 0.010 Norm Max 0.134 0.117
Dimension in mm Min 0.25 2.73 0.17 0.09 Norm 2.85 0.22 Max 3.40 2.97 0.27 0.20
0.107 0.112
0.007 0.009 0.011 0.004 0.008
0.906 0.913 0.921 23.00 23.20 23.40 0.783 0.787 0.791 19.90 20.00 20.10 0.669 0.677 0.685 17.00 17.20 17.40 0.547 0.551 0.555 13.90 14.00 14.10 0.020 BSC 0.029 0.035 0.041 0.063 BSC 0o 0.004 7o 0o 0.73 0.50 BSC 0.88 1.60 BSC 0.10 7o 1.03
E
E
E1 e L 128 39 L1 y 1 e B 38 z
See Detail B See Detail A Seating Plane
A1
y
Note: 1.Dimension D1 & E1 do not include mold protrusion. But mold mismatch is included. Allowable protrusion is .25mm/.010" per side. 2.Dimension B does not include dambar protrusion. Allowable dambar protrusion .08mm/.003". Total in excess of the B dimemsion at maximum material condition. Dambar cannot be located on the lower radius or the foot. 3.Controlling dimension : Millimeter.
A2
A
B
With Plating Gage Plane L z Base Metal L1 Detail A Detail B
C
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MTD505 Revision 1.2 14/04/2000

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